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19-3954; Rev 0; 1/06
21-Bit Deserializers with Programmable Spread Spectrum and DC Balance
General Description
The MAX9242/MAX9244/MAX9246 deserialize three LVDS serial-data inputs into 21 single-ended LVCMOS/ LVTTL outputs. A separate parallel-rate LVDS clock provides the timing for deserialization. The MAX9242/ MAX9244/MAX9246 feature spread-spectrum capability, allowing the output data and clock frequency to spread over a specified range to reduce EMI. The single-ended data and clock outputs are programmable for a frequency spread of 2%, 4%, or no spread. The spread-spectrum function is also available when the MAX9242/MAX9244/ MAX9246 operate in non-DC-balanced mode. The modulation rate of the spread is 32kHz for a 33MHz LVDS clock input and scales linearly with frequency. The singleended outputs have a separate supply, allowing +1.8V to +5V output logic levels. The MAX9242/MAX9244/MAX9246 feature programmable DC balance, allowing isolation between a serializer and deserializer using AC-coupling. The MAX9242/ MAX9244/MAX9246 operate with the MAX9209/ MAX9213 serializers and are available with a risingedge strobe (MAX9242) or falling-edge strobe (MAX9244/MAX9246). The LVDS inputs meet ISO 10605 ESD specifications with 30kV Air-Gap Discharge and 6kV Contact Discharge ratings. The MAX9242/MAX9244/MAX9246 are available in a 48-pin TSSOP package and operate over the -40C to +85C temperature range.
Features
Programmable 4%, 2%, or OFF Spread-Spectrum Output for Reduced EMI Programmable DC-Balanced or Non-DC-Balanced Modes DC Balance Allows AC-Coupling for Wider Input Common-Mode Voltage Range Spread Spectrum Operates in DC-Balanced or Non-DC-Balanced Mode / 4 Deskew by Oversampling (MAX9242/MAX9244) 16MHz-to-34MHz (DC-Balanced) and 20MHz-to40MHz (Non-DC-Balanced) Operation (MAX9242/MAX9244) 6MHz-to-18MHz (DC-Balanced) and 8MHz-to-20MHz (Non-DC-Balanced) Operation (MAX9246) Rising-Edge (MAX9242) or Falling-Edge (MAX9244/MAX9246) Output Strobe High-Impedance Outputs when PWRDWN is Low Allow Output Busing Fail-Safe Inputs in Non-DC-Balanced Mode Separate Output Supply Allows Interface to +1.8V, +2.5V, +3.3V, and +5V Logic LVDS Inputs Meet ISO 10605 ESD Protection at 30kV Air-Gap Discharge and 6kV Contact Discharge LVDS Inputs Meet IEC 61000-4-2 Level 4 ESD Protection at 15kV Air-Gap Discharge and 8kV Contact Discharge LVDS Inputs Conform to ANSI TIA/EIA-644 Standard +3.3V Main Power Supply
MAX9242/MAX9244/MAX9246
Applications
Automotive Navigation Systems Automotive DVD Entertainment Systems Digital Copiers Laser Printers
Selector Guide
FREQUENCY RANGE PART STROBE EDGE Rising Falling Falling OVERSAMPLING Yes Yes No NON-DC BALANCE (MHz) 20 to 40 20 to 40 8 to 20 DC BALANCE (MHz) 16 to 34 16 to 34 6 to 18
Ordering Information
PART MAX9242EUM MAX9244EUM MAX9246EUM TEMP RANGE -40C to +85C -40C to +85C -40C to +85C PIN-PACKAGE 48 TSSOP 48 TSSOP 48 TSSOP PKG CODE U48-1 U48-1 U48-1
MAX9242 MAX9244 MAX9246
Devices are available in lead-free packaging. Specify lead free by adding a + symbol at the end of the part number when ordering. Pin Configuration appears at end of data sheet. ________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
21-Bit Deserializers with Programmable Spread Spectrum and DC Balance MAX9242/MAX9244/MAX9246
ABSOLUTE MAXIMUM RATINGS
(All voltages referenced to GND.) VCC, LVDSVCC, PLLVCC .......................................-0.5V to +4.0V VCCO......................................................................-0.5V to +6.0V RxIN_, RxCLKIN_ ..................................................-0.5V to +4.0V PWRDWN ..............................................................-0.5V to +6.0V SSG, DCB...................................................-0.5V to (VCC + 0.5V) RxOUT_, RxCLKOUT ...............................-0.5V to (VCCO + 0.5V) Continuous Power Dissipation (TA = +70C) 48-Pin TSSOP (derate 16mW/C above +70C) ........1282mW ESD Protection Human Body Model (RD = 1.5k, CS = 100pF) All Pins to GND .............................................................2.5kV IEC 61000-4-2 (RD = 330, CS = 150pF) LVDS Inputs to GND (Air-Gap Discharge).....................15kV LVDS Inputs to GND (Contact Discharge).......................8kV ISO 10605 (RD = 2.0k, CS = 330pF) LVDS Inputs to GND (Air-Gap Discharge).....................30kV LVDS Inputs to GND (Contact Discharge).......................6kV Operating Temperature Range ...........................-40C to +85C Storage Temperature Range .............................-65C to +150C Junction Temperature ......................................................+150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VCC = LVDSVCC = PLLVCC = +3.0V to +3.6V, VCCO = +3.0V to +5.5V, PWRDWN = high; SSG = high, open, or low; DCB = high or low, differential input voltage |VID| = 0.05V to 1.2V, input common-mode voltage VCM = |VID / 2| to 2.4V - |VID / 2|, unless otherwise noted. Typical values are at VCC = VCCO = LVDSVCC = PLLVCC = +3.3V, |VID| = 0.2V, VCM = +1.25V, TA = +25C.) (Notes 1, 2)
PARAMETER POWER SUPPLY Power-Supply Range Output-Supply Range VCC, LVDSVCC, PLLVCC VCCO DC-balanced mode (SSG = low) CL = 8pF, worst-case pattern, VCC = VCCO = 3.0V to 3.6V, Figure 2 (MAX9242, MAX9244) Non-DC-balanced mode (SSG = low) 16MHz 34MHz 20MHz 33MHz 40MHz DC-balanced mode 16MHz (SSG = high or open) 34MHz Non-DC-balanced 33MHz mode (SSG = high or open) 40MHz 20MHz 3.0 1.8 45 72 59 80 93 57 93 71 98 115 3.6 5.5 61 96 79 106 123 78 125 96 129 145 mA V V SYMBOL CONDITIONS MIN TYP MAX UNITS
Worst-Case Supply Current
ICCW
2
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21-Bit Deserializers with Programmable Spread Spectrum and DC Balance
DC ELECTRICAL CHARACTERISTICS (continued)
(VCC = LVDSVCC = PLLVCC = +3.0V to +3.6V, VCCO = +3.0V to +5.5V, PWRDWN = high; SSG = high, open, or low; DCB = high or low, differential input voltage |VID| = 0.05V to 1.2V, input common-mode voltage VCM = |VID / 2| to 2.4V - |VID / 2|, unless otherwise noted. Typical values are at VCC = VCCO = LVDSVCC = PLLVCC = +3.3V, |VID| = 0.2V, VCM = +1.25V, TA = +25C.) (Notes 1, 2)
PARAMETER SYMBOL CONDITIONS 6MHz DC-balanced mode (SSG = low) 8MHz 18MHz 8MHz Non-DC-balanced CL = 8pF, worst-case pattern, mode (SSG = low) VCC = VCCO = 3.0V to 3.6V, Figure 2 DC-balanced mode (MAX9246) (SSG = high or open) Non-DC-balanced mode (SSG = high or open) Power-Down Supply Current High-Level Input Voltage Low-Level Input Voltage Input Current Input Clamp Voltage ICCZ VIH VIL IIN VCL PWRDWN = high or low level ICL = -18mA PWRDWN = low 2.0 -0.3 -20 -1.5 VCC + 0.3 +10 +0.8 +20 10MHz 20MHz 6MHz 8MHz 18MHz 8MHz 10MHz 20MHz MIN TYP 27 30 43 33 37 52 32 38 57 41 46 66 MAX 41 45 61 47 52 73 47 57 81 58 65 92 50 5.5 +0.8 +20 A V V A V mA UNITS
MAX9242/MAX9244/MAX9246
Worst-Case Supply Current
ICCW
5V-TOLERANT LOGIC INPUT (PWRDWN)
THREE-LEVEL LOGIC INPUTS (DCB, SSG) High-Level Input Voltage Mid-Level Input Current Low-Level Input Voltage Input Current Input Clamp Voltage VIH IIM VIL IIN VCL DCB, SSG = high or low level, PWRDWN = high or low ICL = -18mA DCB, SSG open or connected to a driver with output in high-impedance state (Note 3) 2.5 -10 -0.3 -20 -1.5 VCCO - 0.1 RxCLKOUT (Note 4) IOH = -2mA RxOUT_ IOL = 100A Low-Level Output Voltage VOL IOL = 2mA RxCLKOUT (Note 4) RxOUT_ VCCO - 0.25 VCCO - 0.43 0.1 0.2 0.26 V V V A V A V
SINGLE-ENDED OUTPUTS (RxOUT_, RxCLKOUT) IOH = -100A High-Level Output Voltage VOH
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3
21-Bit Deserializers with Programmable Spread Spectrum and DC Balance MAX9242/MAX9244/MAX9246
DC ELECTRICAL CHARACTERISTICS (continued)
(VCC = LVDSVCC = PLLVCC = +3.0V to +3.6V, VCCO = +3.0V to +5.5V, PWRDWN = high; SSG = high, open, or low; DCB = high or low, differential input voltage |VID| = 0.05V to 1.2V, input common-mode voltage VCM = |VID / 2| to 2.4V - |VID / 2|, unless otherwise noted. Typical values are at VCC = VCCO = LVDSVCC = PLLVCC = +3.3V, |VID| = 0.2V, VCM = +1.25V, TA = +25C.) (Notes 1, 2)
PARAMETER High-Impedance Output Current Output Short-Circuit Current (Note 5) LVDS INPUTS (RxIN_, RxCLKIN_) Differential Input High Threshold Differential Input Low Threshold Input Current Power-Off Input Current Input Resistor 1 Input Resistor 2 VTH VTL IIN+, IIN(Note 6) (Note 6) PWRDWN = high or low PWRDWN = high or low, VCC = VCCO = 0V or open, Figure 1 PWRDWN = high or low, VCC = VCCO = 0V or open, Figure 1 -50 -25 -40 42 246 +25 +40 78 410 50 mV mV A A k k SYMBOL IOZ CONDITIONS PWRDWN = low, VOUT = -0.3V to (VCCO + 0.3V) VCCO = 3.0V to 3.6V, VOUT = 0V VCCO = 4.5V to 5.5V, VOUT = 0V RxCLKOUT (Note 4) RxOUT_ RxCLKOUT (Note 4) RxOUT_ MIN -30 -10 -5 -28 -13 TYP MAX +30 -40 -20 -75 -37 mA UNITS A
IOS
IINO+, IINO- VCC = VCCO = 0V or open RIN1 RIN2
AC ELECTRICAL CHARACTERISTICS
(VCC = LVDSVCC = PLLVCC = +3.0V to +3.6V, VCCO = +3.0V to +3.6V, CL = 8pF, PWRDWN = high; SSG = high, open, or low; DCB = high or low, differential input voltage |VID| = 0.1V to 1.2V, input common-mode voltage VCM = |VID / 2| to 2.4V - |VID / 2|, unless otherwise noted. Typical values are at VCC = VCCO = LVDSVCC = PLLVCC = +3.3V, |VID| = 0.2V, VCM = +1.25V, TA = +25C.) (Notes 6, 7, 8)
PARAMETER Output Rise Time Output Fall Time SYMBOL CLHT CHLT CONDITIONS 0.1 x VCCO to 0.9 x VCCO, Figure 3 0.9 x VCCO to 0.1 x VCCO, Figure 3 DC-balanced mode, Figure 4 RxIN Skew Margin (Note 9) RSKM RxOUT_ RxCLKOUT RxOUT_ RxCLKOUT 16MHz 34MHz MIN 2.9 2.0 2.1 1.10 2560 900 2500 960 0.35 x RCOP 0.35 x RCOP 0.3 x RCOP 0.45 x RCOP 4.5 + 6.5 + 8.2 + (RCIP / 2) (RCIP / 2) (RCIP / 2) TYP 4.7 3.3 3.0 1.94 3142 1386 3164 1371 ns ns ns ns ns ps MAX 6.5 4.1 4.2 2.70 UNITS ns ns
Non-DC-balanced mode, 20MHz Figure 4 40MHz Figures 5a, 5b Figures 5a, 5b Figures 5a, 5b Figures 5a, 5b SSG = low, Figures 6a, 6b
RxCLKOUT High Time RxCLKOUT Low Time RxOUT Setup to RxCLKOUT RxOUT Hold from RxCLKOUT RxCLKIN to RxCLKOUT Delay
RCOH RCOL RSRC RHRC RCCD
4
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21-Bit Deserializers with Programmable Spread Spectrum and DC Balance
AC ELECTRICAL CHARACTERISTICS (continued)
(VCC = LVDSVCC = PLLVCC = +3.0V to +3.6V, VCCO = +3.0V to +3.6V, CL = 8pF, PWRDWN = high; SSG = high, open, or low; DCB = high or low, differential input voltage |VID| = 0.1V to 1.2V, input common-mode voltage VCM = |VID / 2| to 2.4V - |VID / 2|, unless otherwise noted. Typical values are at VCC = VCCO = LVDSVCC = PLLVCC = +3.3V, |VID| = 0.2V, VCM = +1.25V, TA = +25C.) (Notes 6, 7, 8)
PARAMETER Deserializer Phase-LockedLoop Set Deserializer Power-Down Delay Deserializer Phase-LockedLoop Set from SSG Change SYMBOL RPLLS RPDD RPLLS2 Figure 7 Figure 8 Figure 9 Maximum output frequency Minimum output frequency Maximum output frequency Minimum output frequency fRxCLKIN + 3.6% fRxCLKIN - 4.4% fRxCLKIN + 1.8% fRxCLKIN - 2.2% fRxCLKIN fRxCLKIN / 1016 fRxCLKIN + 4.0% fRxCLKIN - 4.0% fRxCLKIN + 2.0% fRxCLKIN - 2.0% CONDITIONS MIN TYP MAX 65,600 x RCIP 100 32,800 x RCIP fRxCLKIN + 4.4% fRxCLKIN - 3.6% fRxCLKIN + 2.2% fRxCLKIN - 1.8% fRxCLKIN Hz MHz UNITS ns ns ns
MAX9242/MAX9244/MAX9246
SSG = high, Figure 10 Spread-Spectrum Output Frequency fRxCLKOUT SSG = open, Figure 10 SSG = low Spread-Spectrum Modulation Frequency fSSM Figure 10
Note 1: Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground, except VTH and VTL. Note 2: Maximum and minimum limits over temperature are guaranteed by design and characterization. Devices are production tested at TA = +25C. Note 3: To provide a mid level, leave the input open, or, if driven, put driver in high impedance. High-impedance leakage current must be less than 10A. Note 4: RxCLKOUT limits are scaled based on RxOUT_ measurements, design, and characterization data. Note 5: One output shorted at a time. Current out of the pin. Note 6: VTH, VTL, and AC parameters are guaranteed by design and characterization, and are not production tested. Limits are set at 6 sigma. Note 7: CL includes probe and test jig capacitance. Note 8: RCIP is the period of RxCLKIN. RCOP is the period of RxCLKOUT. Note 9: RSKM is measured with less than 150ps cycle-to-cycle jitter on RxCLKIN.
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5
21-Bit Deserializers with Programmable Spread Spectrum and DC Balance MAX9242/MAX9244/MAX9246
Test Circuits/Timing Diagrams
VCC
RIN2
FAIL-SAFE COMPARATOR RCOP RxIN_ + OR RxCLKIN+ VCC - 0.3V
RxIN_ + OR RxCLKIN+
RxCLKOUT
RIN1
RIN1 1.2V ODD RxOUT EVEN RxOUT
RIN1
RIN1
RxIN_ - OR RxCLKINNON-DC-BALANCED MODE
RxIN_ - OR RxCLKINDC-BALANCED MODE
Figure 1. LVDS Input Circuits
Figure 2. Worst-Case Test Pattern
90%
90%
RxOUT_ OR RxCLKOUT
RxOUT_ OR RxCLKOUT 8pF
10%
10%
CLHT
CHLT
Figure 3. Output Load and Transition Times
IDEAL SERIAL BIT TIME 1.3V
RCOP RxCLK OUT 0.8V
1.1V RSKM IDEAL MIN MAX INTERNAL STROBE RSKM IDEAL
2.0V 0.8V RCOL RSRC
2.0V RCOH RHRC 2.0V 0.8V
2.0V
RxOUT_
2.0V 0.8V
Figure 4. LVDS Receiver Input Skew Margin
Figure 5a. Rising-Edge Output Setup/Hold and High/Low Times
6
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21-Bit Deserializers with Programmable Spread Spectrum and DC Balance
Test Circuits/Timing Diagrams (continued)
RCOP
MAX9242/MAX9244/MAX9246
RCIP RxCLKIN
0.8V 0.8V RCOL RHRC 2.0V 0.8V
RxCLKOUT
2.0V 0.8V RCOH RSRC
2.0V
VID = 0V RCCD 1.5V RxCLKOUT
RxOUT_
2.0V 0.8V
Figure 6a. Clock-IN to Clock-OUT Delay (MAX9244/MAX9246) Figure 5b. Falling-Edge Output Setup/Hold and High/Low Times
2V RCIP PWRDWN 3V VCC RCCD RxCLKOUT 1.5V RxCLKIN RPLLS
+
RxCLKIN VID = 0
-
Figure 6b. Clock-IN to Clock-OUT Delay (MAX9242)
RxCLKOUT
1.5V HIGH IMPEDANCE
PWRDWN 1.5V
Figure 7. Phase-Locked-Loop Set Time
RxCLKIN
RPDD RxOUT_ RxCLKOUT
1.5V
HIGH IMPEDANCE
Figure 8. Power-Down Delay
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7
21-Bit Deserializers with Programmable Spread Spectrum and DC Balance MAX9242/MAX9244/MAX9246
Test Circuits/Timing Diagrams (continued)
2.5V SSG 0.8V OPEN OR LESS THAN 10A LEAKAGE
RPLLS2
RxCLKIN_
RxCLKOUT
RxOUT_
TIMING SHOWN FOR FALLING-EDGE STROBE (MAX9244/MAX9246) PWRDWN = HIGH
Figure 9. Phase-Locked-Loop Set Time from SSG Change
FREQUENCY 1 / fSSM
fRxCLKOUT (MAX)
fRxCLKIN
TIME
fRxCLKOUT (MIN)
Figure 10. Simplified Modulation Profile
8
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21-Bit Deserializers with Programmable Spread Spectrum and DC Balance
Typical Operating Characteristics
(VCC = PLLVCC = LVDSVCC = VCCO = +3.3V, CL = 8pF, PWRDWN = high, differential input voltage |VID| = 0.2V, input common-mode voltage VCM = 1.2V, TA = +25C, MAX9244, unless otherwise noted.)
WORST-CASE AND PRBS SUPPLY CURRENT vs. FREQUENCY (NON-DC-BALANCED MODE, NO SPREAD)
MAX9242 toc01
MAX9242/MAX9244/MAX9246
WORST-CASE AND PRBS SUPPLY CURRENT vs. FREQUENCY (DC-BALANCED MODE, NO SPREAD)
MAX9242 toc02
WORST-CASE AND PRBS SUPPLY CURRENT vs. FREQUENCY (DC-BALANCED MODE, 2% SPREAD)
MAX9242 toc03
100 90 SUPPLY CURRENT (mA) 80 70 60 50 40 30 15 20 25 30 35 27 - 1 PRBS
100 90 SUPPLY CURRENT (mA) 80 WORST-CASE PATTERN 70 60 50 40 30 27 - 1 PRBS
100 90 SUPPLY CURRENT (mA) 80 70 60 50 40 30 27 - 1 PRBS WORST-CASE PATTERN
WORST-CASE PATTERN
40
15
20
25
30
35
40
15
20
25
30
35
40
FREQUENCY (MHz)
FREQUENCY (MHz)
FREQUENCY (MHz)
WORST-CASE AND PRBS SUPPLY CURRENT vs. FREQUENCY (DC-BALANCED MODE, 4% SPREAD)
MAX9242 toc04
RxOUT_TRANSITION TIME vs. OUTPUT SUPPLY VOLTAGE (VCCO)
12 10 8 6 4 2 CHLT 0 CLHT
MAX9242 toc05
100 90 SUPPLY CURRENT (mA) 80 70 60 50 40 30 15 20 25 30 35 27 - 1 PRBS WORST-CASE PATTERN
14 OUTPUT TRANSITION TIME (ns)
40
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
FREQUENCY (MHz)
OUTPUT SUPPLY VOLTAGE (V)
RxCLKOUT POWER SPECTRUM vs. FREQUENCY (RxCLKIN_ = 33MHz, NO SPREAD)
MAX9242 toc06
RxCLKOUT POWER SPECTRUM vs. FREQUENCY (RxCLKIN_ = 33MHz, 2% SPREAD)
MAX9242 toc07
RxCLKOUT POWER SPECTRUM vs. FREQUENCY (RxCLKIN_ = 33MHz, 4% SPREAD)
10 POWER SPECTRUM (dBm) 0 -10 -20 -30 -40 -50 -60 -70 -80 36 30 RESOLUTION BW = 100kHz VIDEO BW = 100kHz ATTENUATION = 50dB 33 FREQUENCY (MHz) 36
MAX9242 toc08
20 10 POWER SPECTRUM (dBm) 0 -10 -20 -30 -40 -50 -60 -70 -80 30 RESOLUTION BW = 100kHz VIDEO BW = 100kHz ATTENUATION = 50dB 33 FREQUENCY (MHz)
20 10 POWER SPECTRUM (dBm) 0 -10 -20 -30 -40 -50 -60 -70 -80 30 33 FREQUENCY (MHz) RESOLUTION BW = 100kHz VIDEO BW = 100kHz ATTENUATION = 50dB
20
36
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21-Bit Deserializers with Programmable Spread Spectrum and DC Balance MAX9242/MAX9244/MAX9246
Typical Operating Characteristics (continued)
(VCC = PLLVCC = LVDSVCC = VCCO = +3.3V, CL = 8pF, PWRDWN = high, differential input voltage |VID| = 0.2V, input common-mode voltage VCM = 1.2V, TA = +25C, MAX9244, unless otherwise noted.)
RxCLKOUT POWER SPECTRUM vs. FREQUENCY (RxCLKIN_ = 16MHz, NO SPREAD)
MAX9242 toc09
RxCLKOUT POWER SPECTRUM vs. FREQUENCY (RxCLKIN_ = 16MHz, 2% SPREAD)
MAX9242 toc10
RxCLKOUT POWER SPECTRUM vs. FREQUENCY (RxCLKIN_ = 16MHz, 4% SPREAD)
10 POWER SPECTRUM (dBm) 0 -10 -20 -30 -40 -50 -60 -70 -80 14 16 FREQUENCY (MHz) 18 RESOLUTION BW = 100kHz VIDEO BW = 100kHz ATTENUATION = 50dB
MAX9242 toc11
20 10 POWER SPECTRUM (dBm) 0 -10 -20 -30 -40 -50 -60 -70 -80 14 RESOLUTION BW = 100kHz VIDEO BW = 100kHz ATTENUATION = 50dB 16 FREQUENCY (MHz)
20 10 POWER SPECTRUM (dBm) 0 -10 -20 -30 -40 -50 -60 -70 -80 14 RESOLUTION BW = 100kHz VIDEO BW = 100kHz ATTENUATION = 50dB 16 FREQUENCY (MHz)
20
18
18
RxOUT_ POWER SPECTRUM vs. FREQUENCY (RxCLKIN_ = 33MHz, NO SPREAD)
MAX9242 toc12
RxOUT_ POWER SPECTRUM vs. FREQUENCY (RxCLKIN_ = 33MHz, 2% SPREAD)
MAX9242 toc13
RxOUT_ POWER SPECTRUM vs. FREQUENCY (RxCLKIN_ = 33MHz, 4% SPREAD)
10 POWER SPECTRUM (dBm) 0 -10 -20 -30 -40 -50 -60 -70 -80 15.0 RESOLUTION BW = 100kHz VIDEO BW = 100kHz ATTENUATION = 50dB 16.5 FREQUENCY (MHz) 18.0
MAX9242 toc14
20 10 POWER SPECTRUM (dBm) 0 -10 -20 -30 -40 -50 -60 -70 -80 15.0 RESOLUTION BW = 100kHz VIDEO BW = 100kHz ATTENUATION = 50dB 16.5 FREQUENCY (MHz)
20 10 POWER SPECTRUM (dBm) 0 -10 -20 -30 -40 -50 -60 -70 -80 15.0 16.5 FREQUENCY (MHz) RESOLUTION BW = 100kHz VIDEO BW = 100kHz ATTENUATION = 50dB
20
18.0
18.0
RxOUT_ POWER SPECTRUM vs. FREQUENCY (RxCLKIN_ = 16MHz, NO SPREAD)
MAX9242 toc15
RxOUT_ POWER SPECTRUM vs. FREQUENCY (RxCLKIN_ = 16MHz, 2% SPREAD)
MAX9242 toc16
RxOUT_ POWER SPECTRUM vs. FREQUENCY (RxCLKIN_ = 16MHz, 4% SPREAD)
10 POWER SPECTRUM (dBm) 0 -10 -20 -30 -40 -50 -60 -70 -80 9 7 8 FREQUENCY (MHz) 9 RESOLUTION BW = 100kHz VIDEO BW = 100kHz ATTENUATION = 50dB
MAX9242 toc17
20 10 POWER SPECTRUM (dBm) 0 -10 -20 -30 -40 -50 -60 -70 -80 7 RESOLUTION BW = 100kHz VIDEO BW = 100kHz ATTENUATION = 50dB 8 FREQUENCY (MHz)
20 10 POWER SPECTRUM (dBm) 0 -10 -20 -30 -40 -50 -60 -70 -80 RESOLUTION BW = 100kHz VIDEO BW = 100kHz ATTENUATION = 50dB 7 8 FREQUENCY (MHz)
20
9
10
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21-Bit Deserializers with Programmable Spread Spectrum and DC Balance
Pin Description
PIN 1 2 3, 25, 32, 38, 44 4 5 6 7 8 9 10 11 12 13, 18 14 15 16 17 19, 21 20 22 23 24 26 27 28, 36, 48 29 30 31 33 NAME RxOUT17 RxOUT18 GND RxOUT19 RxOUT20 SSG DCB RxIN0RxIN0+ RxIN1RxIN1+ LVDSVCC LVDSGND RxIN2RxIN2+ RxCLKINRxCLKIN+ PLLGND PLLVCC PWRDWN RxCLKOUT RxOUT0 RxOUT1 RxOUT2 VCCO RxOUT3 RxOUT4 RxOUT5 RxOUT6 Channel 0 Single-Ended Outputs Output Supply Voltage. Bypass each VCCO to GND with 0.1F and 0.001F capacitors in parallel as close to the pin as possible. Channel 0 Single-Ended Outputs Channel 2 Single-Ended Outputs Ground Channel 2 Single-Ended Outputs Three-Level-Logic, Spread-Spectrum Generator Control Input. SSG selects the frequency spread of RxCLKOUT relative to RxCLKIN (see Table 3). Three-Level-Logic, DC-Balance Control Input. DCB selects DC-balanced, non-DC-balanced, or reserved operation (see Table 1). Inverting Channel 0 LVDS Serial-Data Input Noninverting Channel 0 LVDS Serial-Data Input Inverting Channel 1 LVDS Serial-Data Input Noninverting Channel 1 LVDS Serial-Data Input LVDS Supply Voltage. Bypass LVDSVCC to GND with 0.1F and 0.001F capacitors in parallel as close to the pin as possible. LVDS Ground Inverting Channel 2 LVDS Serial-Data Input Noninverting Channel 2 LVDS Serial-Data Input Inverting LVDS Parallel-Rate Clock Input Noninverting LVDS Parallel-Rate Clock Input PLL Ground PLL Supply Voltage. Bypass PLLVCC to GND with 0.1F and 0.001F capacitors in parallel as close to the pin as possible. 5V-Tolerant LVTTL/LVCMOS Power-Down Input. PWRDWN is internally pulled down to GND. Outputs are high impedance when PWRDWN = low or open. Parallel-Rate Clock Single-Ended Output. The MAX9242 has a rising-edge strobe. The MAX9244/MAX9246 have a falling-edge strobe. FUNCTION
MAX9242/MAX9244/MAX9246
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21-Bit Deserializers with Programmable Spread Spectrum and DC Balance MAX9242/MAX9244/MAX9246
Pin Description (continued)
PIN 34 35 37 39 40 41 42 43 45 46 47 NAME RxOUT7 RxOUT8 RxOUT9 RxOUT10 RxOUT11 RxOUT12 VCC RxOUT13 RxOUT14 RxOUT15 RxOUT16 Channel 2 Single-Ended Outputs Digital Supply Voltage. Bypass VCC to GND with 0.1F and 0.001F capacitors in parallel as close to the pin as possible. Channel 1 Single-Ended Output Channel 1 Single-Ended Outputs FUNCTION
Functional Diagram
CHANNEL 0 RxIN0+ SERIAL-TO-PARALLEL RxIN0CHANNEL 1 RxIN1+ SERIAL-TO-PARALLEL RxIN1CHANNEL 2 RxIN2+ SERIAL-TO-PARALLEL RxIN27x OR 9x STROBES RxCLKIN+ PLL1 RxCLKINDCB FIFO CONTROL PARALLEL CLOCK CLK IN CLK OUT 7 7 RxOUT14-RxOUT20 7 FIFO 7 RxOUT7-RxOUT13 7 7 RxOUT0-RxOUT6
MAX9242/ MAX9244/ MAX9246
SPREADSPECTRUM PLL (SSPLL)
RxCLKOUT
PWRDWN
SSG
12
______________________________________________________________________________________
21-Bit Deserializers with Programmable Spread Spectrum and DC Balance
Detailed Description
The MAX9242/MAX9244/MAX9246 deserialize three LVDS serial-data inputs into 21 single-ended LVCMOS/ LVTTL outputs. The outputs are programmable for no spread or for a spread of 2% or 4%, relative to the LVDS input clock frequency. The MAX9242/MAX9244 operate at a parallel clock frequency of 16MHz to 34MHz in DC-balanced mode and 20MHz to 40MHz in non-DCbalanced mode. The MAX9246 operates at a 6MHz-to18MHz parallel clock frequency in DC-balanced mode and 8MHz-to-20MHz parallel clock frequency in non-DCbalanced mode. DC-balanced or non-DC-balanced operation is controlled by the DCB input. The MAX9242 has a rising-edge strobe and the MAX9244/MAX9246 have a falling-edge strobe. Data coding by the MAX9209/MAX9213 serializers (that are companion devices to the MAX9242/MAX9244/ MAX9246 deserializers) limits the imbalance of ones and zeros transmitted on each channel. If +1 is assigned to each binary 1 transmitted and -1 is assigned to each binary 0 transmitted, the variation in the running sum of assigned values is called the digital sum variation (DSV). The maximum DSV for the data channels is 10. At most, 10 more zeros than ones, or 10 more ones than zeros, are ever transmitted. The maximum DSV for the clock channel is 5. Limiting the DSV and choosing the correct coupling capacitors maintain differential signal amplitude and reduces jitter due to droop on AC-coupled links. To obtain DC balance on the data channels, the serializer parallel data is inverted or not inverted, depending on the sign of the digital sum at the word boundary. Two complementary bits are appended to each group of 7 parallel-input data bits to indicate to the MAX9242/ MAX9244/MAX9246 deserializer whether the data bits are inverted (see Figures 11 and 12). The deserializer restores the original state of the parallel data. The LVDS clock signal alternates duty cycles of 4/9 and 5/9 to maintain DC balance.
MAX9242/MAX9244/MAX9246
DC Balance (DCB)
DC-balanced or non-DC-balanced operation is controlled by the DCB input (see Table 1). In the non-DCbalanced mode, each channel deserializes 7 bits every cycle of the parallel clock. In DC-balanced mode, 9 bits are deserialized every clock cycle (7 data bits + 2 DC-balanced bits). The highest serial-data rate on each channel in DC-balanced mode is 34MHz x 9 = 306Mbps. In non-DC-balanced mode, the maximum data rate is 40MHz x 7 = 280Mbps.
Spread-Spectrum Generator (SSG)
The MAX9242/MAX9244/MAX9246 single-ended data and clock outputs are programmable for a variation of 2% or 4% around the LVDS input clock frequency. The modulation rate of the frequency variation is 32.48kHz for a 33MHz LVDS clock input and scales linearly with the input clock frequency (see Table 2). The spread spectrum can also be turned off. The output spread is controlled through the SSG input (see Table 3).
Table 1. DCB Function
DCB INPUT LEVEL High Mid Low FUNCTION Non-DC-balanced mode Reserved DC-balanced mode
+ RxCLKIN CYCLE N - 1 TxIN15 RxIN2 TxIN14 TxIN20 TxIN19 TxIN18 CYCLE N TxIN17 TxIN16 TxIN15 TxIN14 TxIN20 TxIN19 CYCLE N + 1 TxIN18 TxIN17 TxIN16 TxIN15 TxIN14
TxIN8 RxIN1
TxIN7
TxIN13
TxIN12
TxIN11
TxIN10
TxIN9
TxIN8
TxIN7
TxIN13
TxIN12
TxIN11
TxIN10
TxIN9
TxIN8
TxIN7
TxIN1 RxIN0
TxIN0
TxIN6
TxIN5
TxIN4
TxIN3
TxIN2
TxIN1
TxIN0
TxIN6
TxIN5
TxIN4
TxIN3
TxIN2
TxIN1
TxIN0
TxIN_ IS DATA FROM THE SERIALIZER.
Figure 11. Deserializer Serial Input in Non-DC-Balanced Mode ______________________________________________________________________________________ 13
21-Bit Deserializers with Programmable Spread Spectrum and DC Balance MAX9242/MAX9244/MAX9246
+ RxCLKIN CYCLE N - 1 DCA2 RxIN2 DCB2 TxIN20 TxIN19 TxIN18 CYCLE N TxIN17 TxIN16 TxIN15 TxIN14 DCA2 DCB2 TxIN20 TxIN19 TxIN18 CYCLE N + 1 TxIN17 TxIN16 TxIN15 TxIN14
DCA1 RxIN1
DCB1
TxIN13
TxIN12
TxIN11
TxIN10
TxIN9
TxIN8
TxIN7
DCA1
DCB1
TxIN13
TxIN12
TxIN11
TxIN10
TxIN9
TxIN8
TxIN7
DCA0 RxIN0
DCB0
TxIN6
TxIN5
TxIN4
TxIN3
TxIN2
TxIN1
TxIN0
DCA0
DCB0
TxIN6
TxIN5
TxIN4
TxIN3
TxIN2
TxIN1
TxIN0
TxIN_, DCA_, AND DCB_ ARE DATA FROM THE SERIALIZER.
Figure 12. Deserializer Serial Input in DC-Balanced Mode
Table 2. Modulation Rate
fRxCLKIN (MHz) 6 8 10 16 18 20 33 34 40 fM (kHz) = fRxCLKIN / 1016 5.91 7.87 9.84 15.75 17.72 19.68 32.48 33.46 39.37
To select the mid level, leave the input open, or if driven, put the driver output in high impedance. The driver highimpedance leakage current must be less than 10A. Any spread change causes a maximum delay time of 32,800 x RCIP before output data is valid. When the spread amount is changed from 2% to 4% or viceversa, the data outputs go low for one delay time (see Figure 13). Similarly, when the spread is changed from no spread to 2% or 4%, the data outputs go low for one delay time (see Figure 14). The data outputs continue to switch but are not valid when the spread amount is changed from 2% or 4% to no spread (see Figure 15). The spread-spectrum function is also available when the MAX9242/MAX9244/MAX9246 operate in nonDC-balanced mode.
Hot Swap
When the MAX9242/MAX9244/MAX9246 are connected to an active serializer, they synchronize correctly. The PLL control voltage does not saturate in response to high-frequency glitches that may occur during a hot swap. The PWRDWN input on the MAX9242/MAX9244/ MAX9246 does not need to be cycled when these devices are connected to an active serializer.
Table 3. SSG Function
SSG INPUT LEVEL High Mid Low FUNCTION RxCLKOUT frequency spread 4% relative to RxCLKIN RxCLKOUT frequency spread 2% relative to RxCLKIN No spread on RxCLKOUT relative to RxCLKIN
PLL Lock Time
The MAX9242/MAX9244/MAX9246 use two PLLs. The first PLL (PLL1) generates a 7x clock (non-DC-balanced mode) or a 9x clock (DC-balanced mode) from RxCLKIN for deserializing the LVDS inputs. The second PLL (SSPLL) is used for spread-spectrum modulation. During initial power-up, the PLL1 locks, and SSPLL locks immediately after. The PLL lock times are set by an internal counter. The maximum time to lock for each PLL is 32,800 clock periods. Power and clock should be stable to meet the lock time specification. After initialization, if the first PLL loses lock, it locks again and then the
Note: RxOUT_ data outputs are spread because RxCLKOUT strobes the output of the FIFO.
14
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21-Bit Deserializers with Programmable Spread Spectrum and DC Balance MAX9242/MAX9244/MAX9246
SSG 4% OR 2% SPREAD 2% OR 4% SPREAD
RPLLS2 (32,800 x RCIP)
RxCLKOUT
RxOUT_
LOW
Figure 13. Output Waveforms when Spread Amount is Changed
SSG
NO SPREAD
2% OR 4% SPREAD
RPLLS2 (32,800 x RCIP)
RxCLKOUT
RxOUT_
LOW
Figure 14. Output Waveforms when Spread is Added
SSG
4% OR 2% SPREAD
NO SPREAD
RPLLS2 (32,800 x RCIP)
RxCLKOUT
RxOUT_
DATA SWITCHING BUT NOT VALID
Figure 15. Output Waveforms when Spread is Removed
spread-spectrum PLL locks immediately after (see Figure 16). If the spread-spectrum PLL loses lock, it locks again with only one PLL lock delay (see Figure 17).
AC-Coupling Benefits
Bit errors experienced with DC-coupling (Figure 18) can be eliminated by increasing the receiver commonmode voltage range through AC-coupling. AC-coupling
increases the common-mode voltage range of an LVDS receiver to nearly the voltage rating of the capacitor. The typical LVDS driver output is 350mV centered on a 1.25V offset voltage, making single-ended output voltages of 1.425V and 1.075V. An LVDS receiver accepts signals from 0 to 2.4V, allowing approximately 1V commonmode difference between the driver and receiver on a
15
______________________________________________________________________________________
21-Bit Deserializers with Programmable Spread Spectrum and DC Balance MAX9242/MAX9244/MAX9246
RPLLS (65,600 x RCIP)
INTERNAL PLL1 LOCK
INTERNAL SSPLL LOCK
RxCLKOUT
LOW
LOW
RxOUT_
LOW
LOW
Figure 16. Output Waveforms when PLL1 Loses Lock and Locks Again
RPLLS2 (32,800 x RCIP) INTERNAL SSPLL LOCK
RxCLKOUT
RxOUT_
LOW
TIMING SHOWN FOR STABLE CLOCK AND DATA INPUTS
Figure 17. Output Waveforms if Spread-Spectrum PLL Loses Lock and Locks Again
DC-coupled link (2.4V - 1.425V = 0.975V and 1.075V 0V = 1.075V). Common-mode voltage differences may be due to ground potential variation or common-mode noise. If there is more than 1V of difference, the receiver is not guaranteed to read the input signal correctly and may cause bit errors. AC-coupling filters low-frequency ground shifts and common-mode noise and passes high-frequency data. A common-mode voltage difference up to the voltage rating of the coupling capacitor (minus half the differential swing) is tolerated. DC-balanced coding of the data is required to maintain the differential signal amplitude and limit jitter on an AC-coupled link. A capacitor in series with each output of the LVDS driver is sufficient for AC-coupling. However, two capacitors--one at the serializer output and one at the deserializer input--provide protection in case either end of the cable is shorted to a high voltage.
16
Applications Information
Selection of AC-Coupling Capacitors
Voltage droop and the DSV of transmitted symbols cause signal transitions to start from different voltage levels. Because the transition time is finite, starting the signal transition from different voltage levels causes timing jitter. The time constant for an AC-coupled link needs to be chosen to reduce droop and jitter to an acceptable level. The RC network for an AC-coupled link consists of the LVDS receiver termination resistor (RT), the LVDS driver output resistor (RO), and the series AC-coupling capacitors (C). The RC time constant for two equal-value series capacitors is (C x (RT + RO)) / 2 (Figure 19). The RC time constant for four equal-value series capacitors is (C x (RT + RO)) / 4 (Figure 20).
______________________________________________________________________________________
21-Bit Deserializers with Programmable Spread Spectrum and DC Balance MAX9242/MAX9244/MAX9246
MAX9209/MAX9213
TxOUT 7 7:1 RO RT 100 1:7 FIFO TRANSMISSION LINE RxIN 7
MAX9242/MAX9244/MAX9246
7 TxIN 7:1 100 1:7 FIFO
7 RxOUT
7 7:1 100 1:7 FIFO
7
PWRDWN PLL TxCLK IN TxCLK OUT 21:3 SERIALIZER RxCLK IN 100
PLL1 + SSPLL
PWRDWN RxCLK OUT
3:21 DESERIALIZER
Figure 18. DC-Coupled Link, Non-DC-Balanced Mode
RT is required to match the transmission line impedance (usually 100) and RO is determined by the LVDS driver design (the minimum differential output resistance of 78 for the MAX9209/MAX9213 serializers is used in the following example). This condition leaves the capacitor selection to change the system time constant. In the following example, the capacitor value for a 2% droop is calculated. Jitter due to this droop is then calculated assuming a 1ns transition time: C = -(2 x tB x DSV) / (ln (1 - D) x (RT + RO)) (Eq 1) where: C = AC-coupling capacitor (F) tB = bit time (s) DSV = digital sum variation (integer) ln = natural log D = droop (% of signal amplitude) RT = termination resistor () RO = output resistance () Equation 1 is for two series capacitors (Figure 19). The bit time (tB) is the period of the parallel clock divided by 9.
The DSV is 10. See equation 3 for four series capacitors (Figure 20). The capacitor for 2% maximum droop at 16MHz parallel rate clock is: C = -(2 x tB x DSV) / (ln (1 - D) x (RT + RO)) C = -(2 x 6.95ns x 10) / (ln (1 - 0.02) x (100 + 78)) C = 0.038F Jitter due to droop is proportional to the droop and transition time: tJ = tT x D (Eq 2) where: tJ = jitter (s) tT = transition time (s) (0 to 100%) D = droop (% of signal amplitude) Jitter due to 2% droop and assumed 1ns transition time is: tJ = 1ns x 0.02 tJ = 20ps The transition time in a real system depends on the frequency response of the cable driven by the serializer.
17
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21-Bit Deserializers with Programmable Spread Spectrum and DC Balance MAX9242/MAX9244/MAX9246
MAX9209/MAX9213
HIGH-FREQUENCY, CERAMIC SURFACE-MOUNT CAPACITORS CAN ALSO BE PLACED AT THE SERIALIZER INSTEAD OF THE DESERIALIZER. TxOUT 7 (7 + 2):1 RO RT 100 RxIN 7
MAX9242/MAX9244/MAX9246
1:(9 - 2) + FIFO
7 TxIN (7 + 2):1 100
1:(9 - 2) + FIFO
7 RxOUT
7 (7 + 2):1 100
1:(9 - 2) + FIFO
7
PWRDWN PLL TxCLK IN TxCLK OUT 21:3 SERIALIZER RxCLK IN 100
PLL1 + SSPLL
PWRDWN RxCLK OUT
3:21 DESERIALIZER
Figure 19. Two Capacitors per Link, AC-Coupled, DC-Balanced Mode
The capacitor value decreases for a higher frequency parallel clock and for higher levels of droop and jitter. Use high-frequency, surface-mount ceramic capacitors. Equation 1 altered for four series capacitors (Figure 20) is: C = -(4 x tB x DSV) / (ln (1 - D) x (RT + RO)) (Eq 3)
Fail-Safe
The MAX9242/MAX9244/MAX9246 have fail-safe LVDS inputs in non-DC-balanced mode (Figure 1). Fail-safe drives the outputs low when the corresponding LVDS input is open, undriven and shorted, or undriven and parallel terminated. The fail-safe on the LVDS clock input drives all outputs low when power is stable. Failsafe does not operate in DC-balanced mode.
RxCLKIN-) to differential +15mV by connecting a 10k 1% pullup resistor between the noninverting input and LVDSVCC, and a 10k 1% pulldown resistor between the inverting input and ground. These bias resistors, along with the 100 1% tolerant termination resistor, provide +15mV of differential input. The +15mV bias causes some small degradation of RSKM proportional to the slew rate of the clock input. For example, if the clock transitions 250mV in 500ps, the slew rate of 0.5mV/ps reduces RSKM by 30ps.
Unused LVDS Data Inputs
In non-DC-balanced mode, leave unused LVDS data inputs open. In non-DC-balanced mode, the input failsafe circuit drives the corresponding outputs low, and no pullup or pulldown resistors are needed. In DC-balanced mode, at each unused LVDS data input, pull the inverting input up to LVDSVCC using a 10k resistor, and pull the noninverting input down to ground using a 10k resistor. Do not connect a termination resistor. The pullup and pulldown resistors drive the corresponding outputs low and prevent switching due to noise.
Input Bias and Frequency Detection
In DC-balanced mode, the inverting and noninverting LVDS inputs are internally connected to +1.2V through 42k (min) to provide biasing for AC-coupling (Figure 1). To prevent switching due to noise when the clock input is not driven, bias the clock inputs (RxCLKIN+,
18
______________________________________________________________________________________
21-Bit Deserializers with Programmable Spread Spectrum and DC Balance MAX9242/MAX9244/MAX9246
HIGH-FREQUENCY CERAMIC SURFACE-MOUNT CAPACITORS
MAX9209/MAX9213
TxOUT 7 (7 + 2):1 RO RT 100 RxIN
MAX9242/MAX9244/MAX9246
1:(9 - 2) + FIFO
7
7 TxIN (7 + 2):1 100
1:(9 - 2) + FIFO
7 RxOUT
7 (7 + 2):1 100 1:(9 - 2) + FIFO
7
PWRDWN PLL TxCLK IN TxCLK OUT 21:3 SERIALIZER RxCLK IN 100
PLL1 + SSPLL
PWRDWN RxCLK OUT
3:21 DESERIALIZER
Figure 20. Four Capacitors per Link, AC-Coupled, DC-Balanced Mode
Link Power-Up Sequence
The recommended link power-up sequence is to power up the serializer, wait until the serializer PLL locks, and then power up the deserializer. This sequence prevents the deserializer from seeing an undriven or unstable input when powering up.
surface-mount ceramic 0.1F and 0.001F capacitors in parallel as close to the device as possible, with the smallest value capacitor closest to the supply pin.
Cables and Connectors
Interconnect for LVDS typically has a differential impedance of 100. Use cables and connectors that have matched differential impedance to minimize impedance discontinuities. Twisted-pair and shielded twisted-pair cables offer superior signal quality compared to ribbon cable and tend to generate less EMI due to magnetic field canceling effects. Balanced cables pick up noise as common mode, which is rejected by the LVDS receiver.
PWRDWN
Driving PWRDWN low puts the outputs in high impedance, stops the PLL, and reduces supply current to 50A or less. Driving PWRDWN high drives the outputs low until the PLL locks. The outputs of two deserializers can be bused to form a 2:1 mux with the outputs controlled by PWRDWN. Wait 100ns between disabling one deserializer (driving PWRDWN low) and enabling the second one (driving PWRDWN high) to avoid contention of the bused outputs.
Board Layout
Keep the LVTTL/LVCMOS outputs and LVDS input signals separated to prevent crosstalk. A four-layer PC board with separate layers for power, ground, LVDS inputs, and digital signals is recommended. Layout PC board traces for 100 differential characteristic impedance. The trace dimensions depend on the type of
19
Power-Supply Bypassing
There are separate on-chip power domains for digital circuits, outputs, PLL, and LVDS inputs. Bypass each VCC, VCCO, PLLVCC, and LVDSVCC with high-frequency,
______________________________________________________________________________________
21-Bit Deserializers with Programmable Spread Spectrum and DC Balance MAX9242/MAX9244/MAX9246
trace used (microstrip or stripline). Note that two 50 PC board traces do not have 100 differential impedance when brought close together--the impedance goes down when the traces are brought closer. Route the PC board traces for an LVDS channel (there are two conductors per LVDS channel) in parallel to maintain the differential characteristic impedance. Place the termination resistor at the end of the PC board traces within a 1/4 inch of the LVDS receiver input. Avoid vias. If vias must be used, use only one pair per LVDS channel and place the via for each line at the same point along the length of the PC board traces. This way, any reflections will occur at the same time. Do not make vias into test points for ATE. Make LVDS clock and data pairs the same length on the PC board to avoid pair-to-pair skew. Make the PC board traces that make up a differential pair the same length to avoid skew within the differential pair. The incremental current is added to (for VCCO > 3.6V) or subtracted from (for VCCO < 3.6V) the DC Electrical Characteristics table maximum supply current. The internal output buffer capacitance is CINT = 6pF. The worst-case pattern switching frequency of the data outputs is half the switching frequency of the output clock. In the following example, the incremental supply current of the MAX9244 in spread and DC-balanced mode is calculated for VCCO = 5.5V, fC = 34MHz, and CL = 8pF: VI = 5.5V - 3.6V = 1.9V CT = CINT + CL = 6pF + 8pF = 14pF where: II = CTVI 0.5fC x 21 (data outputs) + CTVIfC x 1 (clock output) II = (14pF x 1.9V x 0.5 x 34MHz x 21) + (14pF x 1.9V x 34MHz) II = 9.5mA + 0.9mA = 10.4mA. The maximum supply current in DC-balanced mode for VCC = VCCO = 3.6V at fC = 34MHz is 125mA (from the DC Electrical Characteristics table). Add 10.4mA to get the total approximate maximum supply current at VCCO = 5.5V and VCC = 3.6V. If the output supply voltage is less than VCCO = 3.6V, the reduced supply current can be calculated using the same formula and method. At high switching frequency, high supply voltage, and high capacitive loading, power dissipation can exceed the package power dissipation rating. Do not exceed the maximum package power dissipation rating. See the Absolute Maximum Ratings for maximum package power dissipation capacity and temperature derating.
5V-Tolerant Input
PWRDWN is 5V tolerant and is internally pulled down to GND. SSG and DCB are not 5V tolerant. The input voltage range for SSG and DCB is nominally ground to VCC.
Skew Margin (RSKM)
Skew margin (RSKM) is the time allowed for degradation of the serial-data sampling setup and hold times by sources other than the deserializer. The deserializer sampling uncertainty is accounted for and does not need to be subtracted from RSKM. The main outside contributors of jitter and skew that subtract from RSKM are interconnect intersymbol interference, serializer pulse position uncertainty, and pair-to-pair path skew.
VCCO Output Supply and Power Dissipation
The outputs have a separate supply (VCCO) for interfacing to systems with 1.8V to 5V nominal input logic levels. The DC Electrical Characteristics table gives the maximum supply current for VCCO = 3.6V with 8pF load at several switching frequencies with all outputs switching in the worst-case switching pattern. The approximate incremental supply current for VCCO other than 3.6V with the same 8pF load and worst-case pattern can be calculated using: II = CTVI 0.5fC x 21 (data outputs) + CTVIfC x 1 (clock output) where: II = incremental supply current CT = total internal (CINT) and external (CL) load capacitance VI = incremental supply voltage fC = output clock switching frequency
Rising- or Falling-Edge Output Strobe
The MAX9242 has a rising-edge output strobe, which latches the parallel output data into the next chip on the rising edge of RxCLKOUT. The MAX9244/MAX9246 have a falling-edge output strobe, which latches the parallel output data into the next chip on the falling edge of RxCLKOUT . The deserializer output strobe polarity does not need to match the serializer input strobe polarity.
Three-Level Logic Inputs
SSG and DCB (DCB mid level is reserved) are threelevel-logic inputs. A logic-high input voltage must be greater than +2.5V and a logic-low input voltage must be less than +0.8V. A mid-level logic is recognized by the MAX9242/MAX9244/MAX9246 when the input is left open or connected to a driver in a high-impedance state. A weak inverter on the input stage of SSG and
20
______________________________________________________________________________________
21-Bit Deserializers with Programmable Spread Spectrum and DC Balance
DCB provides the proper mid-level voltage under conditions of low input current. The mid-level input current must not be greater than 10A, and the mid-level logic state cannot be driven with an external voltage source.
MAX9242/MAX9244/MAX9246
50 TO 100 CHARGE-CURRENTLIMIT RESISTOR HIGHVOLTAGE DC SOURCE CS 330pF
RD 2k DISCHARGE RESISTANCE STORAGE CAPACITOR DEVICE UNDER TEST
IEC 61000-4-2 Level 4 and ISO 10605 ESD Protection
The MAX9242/MAX9244/MAX9246 ESD tolerance is rated for Human Body Model, IEC 61000-4-2 and ISO 10605. The ISO 10605 and IEC 61000-4-2 standards specify ESD tolerance for electronic systems. All LVDS inputs on the MAX9242/MAX9244/MAX9246 meet ISO 10605 ESD protection at 30kV Air-Gap Discharge and 6kV Contact Discharge and IEC 61000-4-2 ESD protection at 15kV Air-Gap Discharge and 8kV Contact Discharge. All other pins meet the Human Body Model ESD tolerance of 2.5kV. The Human Body Model discharge components are CS = 100pF and RD = 1.5k (Figure 21). The IEC 61000-4-2 discharge components are CS = 150pF and RD = 330 (see Figure 22). The ISO 10605 discharge components are CS = 330pF and RD = 2k (Figure 23).
Figure 23. ISO 10605 Contact Discharge ESD Test Circuit
Pin Configuration
TOP VIEW
RxOUT17 RxOUT18 GND RxOUT19 RxOUT20 1 2 3 4 5 6 7 48 47 46 45 44 43 42 41 40 39 38 37 VCCO RxOUT16 RxOUT15 RxOUT14 GND RxOUT13 VCC RxOUT12 RxOUT11 RxOUT10 GND RxOUT9 VCCO RxOUT8 RxOUT7 RxOUT6 GND RxOUT5 RxOUT4 RxOUT3 VCCO RxOUT2 RxOUT1 GND
1M CHARGE-CURRENTLIMIT RESISTOR HIGHVOLTAGE DC SOURCE CS 100pF
RD 1.5k DISCHARGE RESISTANCE STORAGE CAPACITOR DEVICE UNDER TEST
SSG DCB
RxIN0- 8 RxIN0+ 9 RxIN1RxIN1+ LVDSVCC LVDSGND RxIN210 11 12 13 14 15 16 17 18 19 20 21 22 23 24
MAX9242/ MAX9244/ MAX9246
36 35 34 33 32 31 30 29 28 27 26 25
Figure 21. Human Body ESD Test Circuit
RxIN2+ RxCLKIN-
R1 50 TO 100 CHARGE-CURRENTLIMIT RESISTOR HIGHVOLTAGE DC SOURCE CS 150pF
R2 330 DISCHARGE RESISTANCE STORAGE CAPACITOR DEVICE UNDER TEST
RxCLKIN+ LVDSGND PLLGND PLLVCC PLLGND PWRDWN RxCLKOUT RxOUT0
Figure 22. IEC 61000-4-2 Contact Discharge ESD Test Circuit
TSSOP
Chip Information
PROCESS: CMOS
______________________________________________________________________________________ 21
21-Bit Deserializers with Programmable Spread Spectrum and DC Balance MAX9242/MAX9244/MAX9246
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
48L TSSOP.EPS
E H
321
N
TOP VIEW
BOTTOM VIEW
SEE DETAIL A
;
b A1 A2 e D
SEATING PLANE
A
C L
c b b1
WITH PLATING
SIDE VIEW
END VIEW
(; )
c1
PARTING LINE BASE METAL
c
0.25
L
DETAIL A
SECTION C-C
NOTES: 1. DIMENSIONS D & E ARE REFERENCE DATUMS AND DO NOT INCLUDE MOLD FLASH. 2. MOLD FLASH OR PROTRUSIONS NOT TO EXCEED 0.15MM ON D SIDE, AND 0.25MM ON E SIDE. 3. CONTROLLING DIMENSION: MILLIMETERS. 4. THIS PART IS COMPLIANT WITH JEDEC SPECIFICATION MO-153, VARIATIONS, ED. 5. "N" REFERS TO NUMBER OF LEADS. 6. THE LEAD TIPS MUST LIE WITHIN A SPECIFIED ZONE. THIS TOLERANCE ZONE IS DEFINED BY TWO PARALLEL PLANES. ONE PLANE IS THE SEATING PLANE, DATUM (-C-), THE OTHER PLANE IS AT THE SPECIFIED DISTANCE FROM (-C-) IN THE DIRECTION INDICATED.
TITLE:
SEMICONDUCTOR
PROPRIETARY INFORMATION
DALLAS
PACKAGE OUTLINE, 48L TSSOP, 6.1mm BODY
APPROVAL DOCUMENT CONTROL NO. REV.
21-0155
B
1
1
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
22 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2006 Maxim Integrated Products
Springer
Printed USA
is a registered trademark of Maxim Integrated Products, Inc.

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